1. Field of Invention
The present invention relates to a transistor drive circuit, and more specifically relates to a transistor drive circuit of a power converter.
2. Description of Related Art
Power converters have been widely used to provide regulated power supplies for computers, home appliances, communication equipments, mobile phones, etc. FIG. 1 shows a power converter for a battery charger. The maximum output voltage and the maximum output current of the power converter are regulated. It includes a transformer 10 having a primary winding NP, a secondary winding NS and an auxiliary winding NA. One terminal of the primary winding NP is coupled to an input voltage VIN. Another terminal of the primary winding NP is connected to a transistor 20. The transistor 20 is applied to switch the transformer 10 and regulate the output of the power converter. A switching control circuit 100 is coupled to the output of the power converter through an optical coupler 70 to generate a switching signal VG for switching the transistor 20. The output of the optical coupler 70 generates a feedback signal VFB connected to a FB terminal of the switching control circuit 100. A resistor 25 is connected from the transistor 20 to ground for detecting the switching current of the transformer 10 and generating a switching current signal. The resistor 25 is further coupled to a VI terminal of the switching control circuit 100. Through a rectifier 30 and capacitors 35, 37, a voltage VS of the secondary winding NS produces an output voltage VO at the output of the power converter. A transistor 60 is connected to control the optical coupler 70. The transistor 60 is further coupled to the output voltage VO via a zener diode 80 and resistors 51, 52 to develop a voltage feedback loop to control the output voltage VO. Furthermore, a resistor 50 is connected to the output of the power converter to detect an output current IO. A transistor 65 is connected to control the optical coupler 70. The transistor 65 is further coupled to the resistor 50 to develop a current feedback loop to control the output current IO. The voltage feedback loop controls the maximum output voltage VO of the power converter under the value of VO—MAX. The current feedback loop regulates the maximum output current IO of the power converter under the value of IO—MAX. FIG. 2 shows the output characteristic of the power converter. The power converter is operated under the constant voltage (CV) mode when the voltage feedback loop dominates the feedback loop. The power converter is operated at the constant current (CC) mode once the current feedback loop is operated.
A resistor 40 is connected to input voltage VIN to charge a capacitor 45 for providing an initial power to the switching control circuit 100. The auxiliary winding NA is used to further supply a power source to the switching control circuit 100 once the switching of the transformer 10 is started. A voltage VA generated at the auxiliary winding NA is correlated to the voltage VS of the secondary winding NS. Through a rectifier 41, the voltage VA will produce a supply voltage VCC correlated to the output voltage VO of the power converter.
The supply voltage VCC is generated at the capacitor 45 that is connedted to a VCC terminal of the switching control circuit 100 to supply power source to the switching control circuit 100. However, the variation of the output voltage VO is wide once the power converter is operated in CC mode, which will cause a significant change at the supply voltage VCC. For example, a 1V˜5V variation of the output voltage VO may cause a change of 6V˜30V at the supply voltage VCC.
FIG. 3 shows a circuit schematic of the switching control circuit 100. The feedback signal VFB is connected to a positive input of a comparator 130 via a level-shift circuit. A transistor 140, resistors 145, 146 develop the level-shift circuit. The negative input of the comparator 130 is coupled to the VI terminal to receive the switching current signal. The output of the comparator 130 is connected to a reset input of a flip-flop 120 to reset the switching signal VG. An oscillation circuit 110 generates a periodic pulse signal PLS to initiate the switching signal VG. The pulse signal PLS is connected to a clock input of the flip-flop 120 via an inverter 115. The output of the inverter 115 is further connected to an input of an AND gate 125 in order to limit the maximum duty cycle of the switching signal VG. The output of the flip-flop 120 is connected to another input of the AND gate 125. The output of the AND gate 125 generates a control signal PWM connected to an input of a drive circuit 200. The drive circuit 200 is utilized to generate the switching signal VG at an OUT terminal of the switching circuit 100 to control the transistor 20.
FIG. 4 shows a circuit schematic of the drive circuit 200. It includes a P-type transistor 210 having a source terminal connected to the supply voltage VCC. A drain terminal of the P-type transistor 210 is connected to the OUT terminal. An NAND gate 230 controls a gate terminal of the P-type transistor 210. The control signal PWM is connected to an input of the NAND gate 230. An N-type transistor 220 has a drain terminal connected to the OUT terminal. A source terminal of the N-type transistor 220 is connected to the ground. An AND gate 240 controls a gate terminal of the N-type transistor 220. The control signal PWM is connected to an input of the AND gate 240 via an inverter 245. A switching signal VG1 is therefore generated at the OUT terminal in response to the control signal PWM. The output of the NAND gate 230 is connected to another input of the AND gate 240. The output of the AND gate 240 is connected to another input of the NAND gate 230 through an inverter 235. The NAND gate 230 and the AND gate 240 protect the P-type transistor 210 and the N-type transistor 220 from cross-conduction. The disadvantage of this circuit is an unlimited output voltage of the switching signal VG1. The voltage of the switching signal VG1 is almost equal to the supply voltage VCC. The supply voltage VCC may be higher than 20V. However, the 20V is the maximum gate-to-source voltage of the transistor in general. The transistor 20 may be permanently damaged when the gate-to-source voltage of transistors 20 is higher than 20V.
FIG. 5 shows another circuit schematic of the drive circuit 200. An N-type transistor 250 has a drain terminal connected to the supply voltage VCC. A source terminal of the N-type transistor 250 is connected to the OUT terminal. An AND gate 270 controls a gate terminal of the N-type transistor 250. The control signal PWM is connected to an input of the AND gate 270. An N-type transistor 260 has a drain terminal connected to the OUT terminal. A source terminal of the N-type transistor 260 is connected to the ground. An AND gate 280 controls a gate terminal of the N-type transistor 260. The control signal PWM is connected to an input of the AND gate 280 via an inverter 285. A switching signal VG2 is therefore generated at the OUT terminal in response to the control signal PWM. The output of the AND gate 270 is connected to another input of the AND gate 280 through an inverter 286. The output of the AND gate 280 is connected to another input of the AND gate 270 through an inverter 275. The AND gate 270 and the AND gate 280 protect the N-type transistor 250 and the N-type transistor 260 from cross-conduction. A voltage clamp device 255, such as a zener diode, is coupled to the gate of the N-type transistor 250. The voltage clamp device 255 clamps the maximum output voltage of the switching signal VG2, which protects the transistor 20 from over-voltage damage. FIG. 6 shows the circuit of the AND gate 270. A current source 271 is connected to the output of the AND gate 270. The drain of transistors 272 and the drain of the transistor 273 are connected the output of the AND gate 270. The gate of transistors 272 and the gate of the transistor 273 are connected to inputs of the AND gate 270. The current source 271 limits the current flowed through the voltage clamp device 255 when the voltage clamp device 255 is enabled. The disadvantage of the circuit shown in FIG. 5 is a low output voltage of the switching signal VG2, particularly when the supply voltage VCC is low. The voltage of the switching single VG2 is given by,VG2=VCC−VGS250  (3)where the VG2 is the voltage of a logic-high switching signal VG2; VGS250 is the gate-to-source threshold voltage of the transistor 250, and is around 2V normally.
Since the supply voltage VCC may be lower than 6V, which may produce a switching signal VG2 lower than 4V. However, a minimum gate-to-source voltage is around 4V that is required to turn on a high-voltage transistor such as the transistor 20. Furthermore, a low gate-to-source voltage will cause a high RDS-ON (drain-to-source ON resistance) of the transistor, which will increase the power losses of the power converter.
Both output drive circuits shown in FIG. 4 and FIG. 5 are inadequate to be used in a wide range of the supply voltage VCC. The main object of the present invention is to overcome the above-mentioned shortcomings.